The present invention relates to a clock adjusting technique and, more particularly, to a technique which is effective especially when applied for coping with the skew in case a clock is fed from one clock source to a plurality of elements. The present invention is effective when used in a computer or a logical LSI composing the computer.
The system such as the computer has its operations speeded up by feeding a common clock from one clock source to a number of LSIs composing the system to latch the data in synchronism with a master clock.
In the system of the prior art, however, the clock feed system is of the so-called "incontinent type", and the distances from the clock source to the individual logical LSIs are different so that clock skews are caused. In order to prevent the latch of the error data due to the skew, therefore, the design of the prior art has been drawn to afford a considerable margin of the latch timing and so on.
Incidentally, the provision of a plurality of phase adjustor means for receiving clocks from a clock source is disclosed in Japanese Patent Laid Open No. 63-231516 (corresponding to U.S. Ser. No. 152,916).
Moreover, the technique for reducing the interclock skews is disclosed on pp. 85 to 90 of "NEC Technical Report" issued in August, 1983 by K.K. Nippon Denki.